A method to make vertical interconnects in a semiconductor substrate is known from WO 2005/099699 A1. In the method trenches are formed in the semiconductor substrate by etching from the first side of the substrate and a cavity is formed by etching from the second side of the substrate in such a way that the trenches and the cavity together form vertical interconnect hole through the substrate. The vertical interconnect hole is given a conductive surface so as to form the vertical interconnect extending from the first surface to the second surface of the semiconductor substrate.
The prior art method uses a two-step etching process to obtain a vertical interconnect hole comprising two parts that are complementary, the first part comprising one or more trenches and the second part comprising a cavity. This method allows that the resolution of the vertical interconnect hole, at least at first side of the semiconductor substrate can be increased independently from that of the dimension on the second side.